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msm6222b-01 ? semiconductor 1/45 fedl6222b-01-01 general description the msm6222b-01 is a dot matrix lcd controller which is fabricated in low power cmos silicon gate technology. character display on the dot matrix character type lcd can be controlled in combination with a 4-bit/8-bit microcontroller. this lsi consists of 16-dot common driver, 40-dot segment driver, display data ram, character generator ram, character generator rom and control circuit. the msm6222b-01 is the equivalent of hitachi's hd44780. there is, however, a slight difference between the two devices as described in the table on the last page. msm6222b-01 is a standard version having 160 characters with lowercase (5 x 7 dots), and 32 characters with uppercase (5 x 10 dots) in this rom. features ? easy interface with an 8-bit or 4-bit microcontroller. ? dot matrix lcd controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots). ? automatic power on reset. ? common signal drivers (16) and segment signal drivers (40). ? can control up to 80 characters when used in combination with msm5259. ? character generator rom for 160 characters with lowercase (5 x 7 dots) and 32 characters with uppercase (5 x 10 dots). ? character patterns are programmable by character generator ram. (lowercase: 5 x 8 dots, 8 kinds, uppercase: 5 x 11 dots, 4 kinds). ? oscillation circuit for external resistor or ceralock. ? 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2 lines; 5 x 7 dots + cursor), selectable. ? clear display even at 1/5 bias, 3.0v lcd driving voltage. ? package options: 80-pin plastic qfp (qfp80-p-1420-0.80-l) (product name: msm6222b-01gs-l) 80-pin plastic qfp (qfp80-p-1420-0.80-bl) (product name: MSM6222B-01GS-BL) ? semiconductor msm6222b-01 dot matrix lcd controller with 16-dot common driver and 40-dot segment driver fedl6222b-01-01 this version: sep. 2001
msm6222b-01 ? semiconductor 2/45 fedl6222b-01-01 block diagram do seg 1~40 40 com 1~16 16 l cp df 16 5 5 5 8 8 7 7 7 8 8 8 8 7 4 4 v dd gnd osc 1 osc 2 e rs r/w db 0 - db 3 db 4 - db 7 v 1 common signal driver 16-bit shift register parallel/ serial conver- sion cursor blink control character generator rom (cg ram) character generator ram (cg ram) display data ram (dd ram) timing generation circuit input/ output buffer instruction register (ir) instruction decoder (id) data register (dr) busy flag (bf) address counter (adc) 40 40 seg- ment signal driver 40-bit latch 40-bit shift register v 2 v 3 v 4 v 5
msm6222b-01 ? semiconductor 3/45 fedl6222b-01-01 pin configuration 50 49 48 47 46 com 4 com 3 com 2 com 1 db 7 seg 39 seg 40 com 16 com 15 com 14 com 13 com 12 com 11 com 10 61 62 63 64 60 59 58 57 56 55 54 53 52 51 com 9 com 8 com 7 com 6 com 5 45 44 43 42 41 db 6 db 5 db 4 db 3 db 2 80 seg 20 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 4 3 2 1 5 6 7 8 9 10 11 12 13 14 seg 19 seg 36 seg 37 seg 38 seg 30 seg 25 seg 24 seg 23 seg 31 seg 29 seg 28 seg 26 seg 27 seg 32 seg 33 seg 34 seg 35 v 2 v 1 osc 2 df db 1 db 0 e r/w rs do v dd cp l v 5 v 4 v 3 seg 8 seg 7 seg 6 seg 5 seg 4 15 16 17 18 19 seg 22 seg 21 seg 3 seg 2 seg 1 gnd osc 1 20 21 22 23 24 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80-pin plastic qfp note: the figure for type l shows the configuration viewed from the marked side of the package.
msm6222b-01 ? semiconductor 4/45 fedl6222b-01-01 pin descriptions symbol i/o r/w i i i i o o o o o o o i/o read/write selection input pin with a built-in pull-up resistor. "h" : read, and "l" : write description rs register selection input pin pin with a built-in pull-up resistor. "h" : data register, and "l" : instruction register e input pin for data input/output between cpu and msm6222b-01 and for instruction register activation. db 0 - db 7 input/output pins for data send/receive between cpu and msm6222b-01. these pins have built-in pull-up resistors. osc 1 osc 2 clock oscillating pins required for internal operation upon receipt of the lcd drive signal and cpu instruction. com 1 - com 16 lcd common signal output pins. seg 1 - seg 40 lcd segment signal output pins. do output pin to be connected to msm5259 to expand the number of characters to be displayed. cp clock output pin used when do pin data output shifts inside of msm5259. l clock output pin for the serially transferred data to be latched to msm5259. df the alternating current signal (display frequency) output pin. v dd power supply pin. gnd ground pin. v 1 , v 2 , v 3 , v 4 , v 5 bias voltage pins to drive the lcd.
msm6222b-01 ? semiconductor 5/45 fedl6222b-01-01 absolute maximum ratings parameter supply voltage symbol condition rating unit applicable pin v dd ta = 25 c C0.3 to + 7.0 v v dd , gnd lcd driving voltage v 1 , v 2 , v 3 v 4 , v 5 ta = 25 c v dd C 9.0 to v dd + 0.3 v v 1 , v 2 , v 3 v 4 , v 5 storage temperature t stg C55 to + 150 c power dissipation p d 500 mw input voltage v i ta = 25 c C0.3 to v dd + 0.3 v r/w, rs, e, db 0 - db 7 osc 1 recommended operating conditions parameter supply voltage symbol condition range unit applicable pin v dd 4.5 to 5.5 v v dd , gnd lcd driving voltage v lcd *1 1/4 bias, v dd Cv 5 *2 3.0 to 8.0 v v dd , v 5 1/5 bias, v dd Cv 5 *3 3.0 to 8.0 v operating temperature t op C20 to + 75 c *1 voltage between v dd and v 5. *2 voltages applicable to v 1 , v 2 , v 3 and v 4 are as follows. v 1 = v dd C 1/4 (v dd C v 5 ) v 2 = v 3 = v dd C 1/2 (v dd - v 5 ) v 4 = v dd C 3/4 (v dd C v 5 ) *3 voltages applicable to v 1 , v 2 , v 3 and v 4 are as follows. v 1 = v dd C 1/5 (v dd C v 5 ) v 2 = v dd C 2/5 (v dd C v 5 ) v 3 = v dd C 3/5 (v dd C v 5 ) v 4 = v dd C 4/5 (v dd C v 5 )
msm6222b-01 ? semiconductor 6/45 fedl6222b-01-01 electrical characteristics dc characteristics parameter "h" input voltage (v dd = 4.5 to 5.5v, ta = C20 to +75 c) symbol condition min. typ. max. unit applicable pin v ih1 2.2 v dd v r/w, rs, e, db 0 - db 7 "l" input voltage v il1 C0.3 0.6 v "h" input voltage v ih2 v dd C 1.0 v dd v osc 1 "l" input voltage v il2 C0.3 1.0 v "h" output voltage v oh1 i o = C0.205ma 2.4 v db 0 - db 7 "l" output voltage v ol1 i o = 1.2ma 0.4 v "h" output voltage v oh2 i o = C40 m a 0.9v dd v do, cp, l, dc, osc 2 "l" output voltage v ol2 i o = 40 m a 0.1v dd v com voltage drop v c i o = 50 m a *1 2.9 v com 1 - com 16 seg voltage drop v s i o = 50 m a *1 3.8 v seg 1 - seg 40 input leakage current i il v i = v ss C1 m a e v i = v dd 1 m a input current i il2 v dd = 5.0v v i = v ss C50 C125 C250 m a r/w, rs db 0 - db 7 v i = v dd , excluding current flowing over pullup resistor and output drive mos 2 m a *1 applicable to the voltage drop (v c ) occurring in pins v dd , v 1 , v 4 , and v 5 to each common pin (com1 to com16) when 50 m a flows in or out of all com and seg pins. also applicable to voltage drop (v s ) occurring in pins v dd , v 2 , v 3 , and v 5 to each seg pin (seg1 to seg40). when output level is at v dd , v 1 or v 2 level, 50 m a flows out, while 50 m a flows in when the output level is at v 3 , v 4 or v 5 level. this occurs when +5v is input to v dd , v 1 , and v 2 , and when C3v is input to v 3 , v 4 , and v 5 .
msm6222b-01 ? semiconductor 7/45 fedl6222b-01-01 v dd = 5.0v, resistor oscillation or external clock input via osc 1 . f osc = 270khz. e is in "l" level. other inputs are open. output pins are all no load. *2 parameter (v dd = 4.5 to 5.5v, ta = C20 to +75 c) symbol condition min. typ. max. unit applicable pin v dd supply current (1) i dd1 0.35 0.6 ma lcd driving bias input voltage v lcd1 1/5 bias 3.0 8.0 v v dd , v 1 , v 2 , v 3 , v 4 , v 5 1/4 bias 3.0 8.0 v dd supply current (2) i dd2 0.55 0.8 ma v lcd2 v dd = 5.0v, ceramic oscillation, f osc = 250khz. e is in "l" level. other pins are open. output pins are all no load. *2 v dd Cv 5 *7 *2 applicable to the current that flows in pin v dd when power is input as follows: v dd = 5v, gnd = 0v, v 1 = 3.4v, v 2 = 1.8v, v 3 = 0.2v, v 4 = C1.4v, and v 5 = C3v. ac characteristics r f = 91k w 2% *3 parameter (v dd = 4.5 to 5.5v, ta = C20 to +75 c) symbol condition min. typ. max. unit applicable pin r f clock oscillation frequency f osc1 175 250 350 khz osc 1 osc 2 clock input frequency f in 125 250 350 khz osc 1 input clock duty f duty 45 50 55 % osc 1 input clock rise time t r 0.2 m s osc 1 input clock fall time t f 0.2 m s osc 1 ceramic filter oscillation frequency f osc 245 250 255 khz osc 1 osc 2 osc 2 is open. input from osc 1 *4 *5 *5 r f = 510k w , c 1 = c 2 = 200 pf, r d = 30k w , and ceralock csb250a. *6
msm6222b-01 ? semiconductor 8/45 fedl6222b-01-01 v lcd is an lcd driving voltage. (for "n" (number of lcd lines), refer to the initial set of the instruction code.) r f =91k w 2% ceralock : csb250a (mfd. by murata mfg.co.) minimum wiring is required between osc 1 and r f and between osc 2 and r f . 0.5v dd 0.5v dd t lw t hw 0.5v dd f duty = t hw / (t hw + t lw ) x 100(%) r f *3 *4 applied to pulse input via osc 1 . osc 1 osc 2 f in waveform *5 applied to pulse input via osc 1 . C1.0v dd 1.0v dd 1.0v v dd C1.0v t r t f *6 osc 1 osc 2 c1 c2 r d r f ceralock please contact the manufacturer when using the ceralock. *7 input the voltage listed in the table below to v 1 - v 5 : f in waveform : 510k w 5% : 30k w 5% : 200pf 10% : 200pf 10% r f r d c 1 c 2 v 1 1-line mode 2-line mode pin v dd C v lcd 4 n (lcd lines) v dd C v lcd 5 v 2 v dd C v lcd 2 v dd C 2v lcd 5 v 3 v dd C v lcd 2 v 4 v 5 v dd C v lcd v dd C 3v lcd 5 v dd C 4v lcd 5 v dd C v lcd v dd C 3v lcd 4
msm6222b-01 ? semiconductor 9/45 fedl6222b-01-01 switching characteristics ? timing for input from the cpu parameter r/w and rs set-up time symbol min. typ. max. unit t b 140 ns e "h" pulse width t w 280 ns r/w and rs holding time t a 10 ns e rise time t r 25 ns e fall time t f 25 ns e "l" pulse width t l 280 ns e cycle time t c 667 ns db 0 to db 7 input data set-up time t i 180 ns db 0 to db 7 input data holding time t h 10 ns (v dd = 4.5 to 5.5v, ta = C20 to +75 c) db 0 - db 7 r/w rs e t r v il v ih v ih v il v il v ih v il v ih input data t c v il t l t a t w v il v ih v il v ih v il t b t f t i t h v il
msm6222b-01 ? semiconductor 10/45 fedl6222b-01-01 ? timing for output to the cpu parameter r/w and rs set-up time symbol min. typ. max. unit t b 140 ns e "h" pulse width t w 280 ns r/w and rs holding time t a 10 ns e rise time t r 25 ns e fall time t f 25 ns e "l" pulse width t l 280 ns e cycle time t c 667 ns db 0 to db 7 data output delay time t d 220 ns db 0 to db 7 data output holding time t o 20 ns (v dd = 4.5 to 5.5v, ta = C20 to +75 c) r/w rs v il e db 0 -db 7 t w v ih v ih v ih v il v oh v ol v oh v ol output data v ih v il t a v ih v il v ih t r t b t d t d v il t l t f t c
msm6222b-01 ? semiconductor 11/45 fedl6222b-01-01 ? timing for output to msm5259 parameter cp "h" pulse width symbol min. typ. max. unit t hw1 800 ns cp "l" pulse width t lw 800 ns do set-up time t s 300 ns do holding time t dh 300 ns l clock set-up time t su 500 ns l clock holding time t ho 100 ns l "h" pulse width t hw2 800 ns df delay time t m C1000 1000 ns (v dd = 4.5 to 5.5v, ta = C20 to +75 c) cp v oh2 v ol2 v oh2 v ol2 t dh t s t hw1 v oh2 v oh2 v oh2 v ol2 v ol2 v ol2 v oh2 v oh2 v oh2 v ol2 v oh2 t m t hw2 t su t ho l do df t lw
msm6222b-01 ? semiconductor 12/45 fedl6222b-01-01 functional description instruction register (ir) and data register (dr) these two registers are selected by the register selector (rs) pin. the dr is selected when the "h" level is input to the rs pin and ir is selected when the "l" level is input. the ir is used to store the address of the display data ram (dd ram) or character generator ram (cg ram) and instruction code. the ir can be written, but not be read by the microcomputer (cpu). the dr is used to write and read the data to and from the dd ram or cg ram. the data written to dr by the cpu is automatically written to the dd ram or cg ram as an internal operation. when an address code is written to ir, the data (of the specified address) is automatically transferred from the dd ram or cg ram to the dr. next, when the cpu reads the dr, it is possible to verify dd ram or cg ram data from the dr data. after the writing of dr by the cpu, the next adress in the dd ram or cg ram is selected to be ready for the next cpu writing. likewise, after the reading out of dr by the cpu, dd ram or cg ram data is read out by the dr to be ready for the next cpu reading. write/read to and from both registers is carried out by the read/write (r/w) pin. table 1 rs and r/w pins functions busy flag (bf) when the busy flag is at "h", it indicates that the msm6222b-01 is engaged in internal operation. when the busy flag is at "h", any new instruction is ignored. when r/w = "h" and rs = "l", the busy flag is output from db 7 . new instruction should be input when busy flag is "l" level. when the busy flag is at "h", the output code of the address counter (adc) is undefined. address counter (adc) the address counter (adc) allocates the address for the dd ram and cg ram write/read and also for the cursor display. when the instruction code for a dd ram address or cg ram address setting is input to ir, after deciding whether it is dd ram or cg ram, the address code is transferred from ir to adc. after writing (reading) the display data to (from) the dd ram or cg ram, the adc is incremented (decremented) by 1 internally. the data of the adc is output to db 0 - db 6 on the conditions that r/w = "h", rs = "l", and bf = "l". l rs function r/w l ir write h l read of busy flag (bf) and address counter (adc) l h dr write h h dr read
msm6222b-01 ? semiconductor 13/45 fedl6222b-01-01 timing generator circuit this circuit is used to generate timing signals to activate internal operations upon receipt of cpu instruction and also from such internal circuits as the dd ram, cg ram, and cg rom. it is designed so that the internal operation caused by accessing from the cpu will not interfere with the internal operation caused by lcd driving. consequently, when data is written from the cpu to dd ram, flickering does not occur in a display area other than the display area where the data is written. in addition, this circuit generates the transfer signal to msm5259 for display character expansion. display data ram (dd ram) this ram is used to store display data of 8-bit character codes (see table 2). dd ram address corresponds to the display position of the lcd. the correspondence between the two is described in the following. dd ram address (set to adc) is expressed in hexadecimal notation as shown below: (1) correspondence between address and display position in the 1-line display mode ? when the msm6222b-01 alone is used, up to 8 characters can be displayed from the first to eighth digit. when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below: 00 first digit (display) 01 2 02 3 03 4 04 5 4e 79 4f 80 leftmost position rightmost position display position dd ram address (hex.) 00 first digit 01 2 02 3 03 4 04 5 05 6 06 7 07 8 4f first digit 00 2 01 3 02 4 03 5 04 6 05 7 06 8 (display shifted to right) first digit 02 2 03 3 04 4 05 5 06 6 07 7 08 8 (display shifted to left) 01 lsb msb db 0 db 6 adc (hex) l l 2a (example) when dd ram address is 2a hlhlh
msm6222b-01 ? semiconductor 14/45 fedl6222b-01-01 ? when the msm6222b-01 is used with one msm5259, up to 16 characters can be displayed from the first to sixteenth digit as shown below: when the display is shifted by instruction, the correspondence between the lcd display and the dd ram address changes as shown below: ? since the msm6222b-01 has a dd ram capacity of up to 80 characters, up to 9 msm5259 devices can be connected to msm6222b-01 so that 80 characters can be displayed. 00 first digit 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 09 10 0a 11 0b 12 0c 13 0d 14 0e 15 0f 16 9 msm5259 (1) display msm6222b-01 display 10 11 18 17 48 49 74 4a 75 4b 76 4c 77 4d 78 4e 79 4f 80 73 msm5259 (9) display msm5259 (2) - (8) display 4f first digit 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 08 10 09 11 0a 12 0b 13 0c 14 0d 15 0e 16 9 msm5259 display msm6222b-01 display (display shifted to right) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 (display shifted to left) 00 first digit 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 09 10 0a 11 0b 12 0c 13 0d 14 0e 15 0f 16 9 msm5259 display msm6222b-01 display
msm6222b-01 ? semiconductor 15/45 fedl6222b-01-01 (2) correspondence between address and display position in the 2-line display mode (note) the last address of the first line is not consecutive to the head address of the second line. ? when msm6222b-01 alone is used, up to 16 characters (8 characters x 2 lines) can be displayed from the first to eighth digit. when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below: ? when the msm6222b-01 is used with one msm5259, up to 32 characters (16 characters x 2 lines) can be displayed from the first to the sixteenth digit. 00 first digit 01 2 02 3 03 4 04 5 40 41 42 43 44 first line second line 05 6 06 7 07 8 45 46 47 msm6222b-01 display 08 09 10 0a 11 0b 12 0c 13 48 49 4a 4b 4c 0d 14 0e 15 0f 16 4d 4e 4f msm5259 display 9 00 first digit 01 2 02 3 03 4 04 5 40 41 42 43 44 first line second line 05 6 06 7 07 8 45 46 47 27 first digit 00 2 01 3 02 4 03 5 67 40 41 42 43 first line second line 04 6 05 7 06 8 44 45 46 (display shifted to right) 01 first digit 02 2 03 3 04 4 05 5 41 42 43 44 45 first line second line 06 6 07 7 08 8 46 47 48 (display shifted to left) 00 first digit 01 2 02 3 03 4 04 - - - - - - 5 26 39 27 40 display position dd ram address (hex.) 40 41 42 43 44 66 67 first line second line
msm6222b-01 ? semiconductor 16/45 fedl6222b-01-01 when the display is shifted by instruction, the correspondence between the lcd display position and the dd ram address changes as shown below: 00 first digit 01 2 02 3 03 4 04 5 40 41 42 43 44 first line second line 05 6 06 7 07 8 45 46 47 msm6222b-01 display 08 09 10 0a 11 0b 12 0c 13 48 49 4a 4b 4c 0d 14 0e 15 27 16 4d 4e 67 msm5259 display 9 (display shifted to right) first digit 01 2 02 3 03 4 04 5 41 42 43 44 first line second line 05 6 06 7 07 8 45 46 47 msm6222b-01 display 08 09 10 0a 11 0b 12 0c 13 48 49 4a 4b 4c 0d 14 0e 15 16 4d 4e msm5259 display 9 (display shifted to left) 10 4f 50 0f ? since the msm6222b-01 has a dd ram capacity of up to 80 characters, up to 4 msm5259 devices can be connected to the msm6222b-01 in the 2-line display mode. character generator rom (cg rom) the cg rom is used to generate 5 x 7 dots (160 kinds) or 5 x 10 dots (32 kinds) character patterns from an 8-bit dd ram character code signal. the correspondence between 8-bit character codes and character patterns is shown in table 2. when the 8-bit character code of the cg rom is written to the dd ram, the character pattern of the cg rom corresponding to the code is displayed on the lcd display position corresponding to the dd ram address. 00 first digit 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 09 10 0a 11 0b 12 0c 13 0d 14 0e 15 0f 16 9 msm5259 (1) display msm6222b-01 display 10 11 - - - - - - 18 17 20 21 34 22 35 23 36 24 37 25 38 26 39 27 40 33 msm5259 (4) display msm5259 (2) - (3) display 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 60 61 62 63 64 65 66 67 first line second line
msm6222b-01 ? semiconductor 17/45 fedl6222b-01-01 table 2 relationship between character codes and characters (character patterns) of msm6222b -01 lower 4 bits upper 4 bits 0000 lsb 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0001 cg ram (1) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (9) (7) (8) (2) # $ % & ( ) * + C . / ! 2 3 4 5 6 7 8 9 : ; < = > ? 1 0 b c d e f g h i j k l m n o a @ r s t u v w x y z [ ] ^ _ q p b c d e f n h i j k l m n o a / r s t u v w x y z { ? } ? ? q p b e m s r g C1 j x n ? ? a q w s p x q r ?
msm6222b-01 ? semiconductor 18/45 fedl6222b-01-01 character generator ram (cg ram) the cg ram is used to display user's original character patterns other than character patterns in the cg rom. the cg ram has a capacity (64 bytes = 512 bits) of writing 8 kinds of characters for 5 x 7 dots and 4 kinds of characters for 5 x 10 dots. when displaying character patterns stored in the cg ram, write 8-bit character codes (00 to 07 or 08 to 0f; hex.) on the left side as shown in table 2. then it is possible to output the character pattern to the lcd display position corresponding to the dd ram address. the following explains how to write and read character patterns to and from the cg ram. (1) when the character pattern is 5 x 7 dots (see table 3-1). ? a method of writing character pattern to the cg ram by cpu: three bits of cg ram addresses 0-2 correspond to the line position of the character pattern. first, set increment or decrement by the cpu, and then input the cg ram address. after this, write character patterns to the cg ram through db 0 - db 7 line by line. db 0 to db 7 correspond to cg ram data 0-7 in table 3-1. it is displayed when "h" is set as input data and is not displayed when "l" is set as input data. since the adc is automatically incremented or decremented by 1 after the writing of data to the cg ram, it is not necessary to set the cg ram address again. the line, in which the cg ram addresses 0-2 are all "h" ("7" in hexadecimal notation), is the cursor position. it is ored with the cursor at the cursor position and displayed to lcd. for this reason, it is necessary to set all input data that become cursor positions to "l". although cg ram data 0-4 bits are output to the lcd as display data, cg ram data bits 5-7 are not output. the latter can be written and read to and from the ram, it is therefore allowed to be used as data ram. ? a method of displaying the cg ram character pattern to the lcd: the cg ram is selected when upper 4 bits of the character codes are all "l". as character code bit 3 is invalid, the display of "0" in table 3-1, is selected by character code "00" (hex.) or "08" (hex.). when the 8-bit character code of the cg ram is written to the dd ram, the character pattern of the cg ram is displayed on the lcd display position corresponding to the dd ram address. (dd ram data, bits 0-2 correspond to cg ram address, bits 3-5.)
msm6222b-01 ? semiconductor 19/45 fedl6222b-01-01 (2) when character pattern is 5 x 10 dots (see table 3-2). ? a method of writing character pattern into the cg ram by the cpu: four bits of cg ram address, bits 0-3, correspond to the line position of the character pattern. first, set increment or decrement with the cpu, and then input the address of the cg ram. after this, write the character pattern code into the cg ram, line by line from db 0 - db 7 . db 0 to db 7 correspond to cg ram data, bits 0-7, in table 3-2. it is displayed when "h" is set as input data, while it is not displayed when "l" is set as input data. as the adc is automatically incremented or decremented by 1 after the writing of data to the cg ram, it is not necessary to set the cg ram address again. the line, the cgram addresses 0-3 of which are "a" in hexadecimal notation, is the cursor position. the cgram data is 0red with the cursor at the cursor position and displayed to lcd. for this reason, it is necessary to set all input data that become cursor positions to "l". when the cg ram data, bits 0-4, and cg ram addresses, bits 0-3, are "0" to "a", they are displayed on the lcd as the display data. when the cg ram data, bits of 5-7, and cg ram, bit data is 0-4 and cg ram address data is "b" to "f", it is not output to the lcd. but in this case, cg ram can be used as ram and it can be written into/read out. so, it can be used as the data ram. ? a method of displaying the cg ram character pattern to the lcd: the cg ram is selected when 4-upper order bits of the character code are all "l". as character code bits 0 and 3 are invalid, the display of " m " is selected by character codes "00", "01", "08", and "09" (hex.) as in table 3-2. when the cg ram character code is written to the dd ram, the cg ram character pattern is displayed on the lcd display position corresponding to the dd ram address. (dd ram data bits 1 and 2 correspond to cg ram address bits 4 and 5.)
msm6222b-01 ? semiconductor 20/45 fedl6222b-01-01 table 3-1 relationship between cg ram data (character pattern), cg ram address and dd ram data when the character pattern is 5 x 7 dots. the example below indicates "oki". x : don't care h l l l l l h l h l l l l l h l h l l l l l h l cg ram address cg ram data (character pattern) dd ram data (character code) h l l l l l h l l h h h h h l l xxxl h h h h h l l ll l l l h h h h l l h h l l h h l h l h l h l h ll h h h h h h h l h l l l l l h l l l l l l l l l xxxl l l l l l l l hl l l l h h h h l l h h l l h h l h l h l h l h hh x llll hhh h ll x llll lll x llll llh l l l h l l l l l l h l h l l l l h l l l h l l h l l l l l h l h h h h h h h l l l h h l l h h l h l h l h l h l l l l h h h h 54 3 21 0 msb 54 3 21 0 6 7 54 3 21 0 6 7 lsb msb lsb msb lsb xxx
msm6222b-01 ? semiconductor 21/45 fedl6222b-01-01 table 3-2 relationship between cg ram data (character pattern), cg ram address and dd ram data when the character pattern is 5 x 10 dots. the examples below indicate m , g and . cg ram address cg ram data (character pattern) dd ram data (character code) l l l l l h l l l l l x l l l l l h l l l l l x l l l l h l l l l l l x l h h h h h l l l l l x xxxl h h h h h h h h l l x l l l l l l l l h h h h h h h h l l l l h h h h l l l l h h h h l l h h l l h h l l h h l l h h l h l h l h l h l h l h l h l h ll x llll llx l l h l l l h l l h l x l l h l l l h l l h l x l l h l l l h l l h l x l l h h h h h h h l l x xxxl l l h h h l l l l l x l l l l l l l l h h h h h h h h l l l l h h h h l l l l h h h h l l h h l l h h l l h h l l h h l h l h l h l h l h l h l h l h lh x llll lhx l l h h l l h l l l l x l l l l l l h l l l l x l l h h l l h l l l l x l l h l h h l l l l l x xxx l l l l l l l l h h h h h h h h l l l l h h h h l l l l h h h h l l h h l l h h l l h h l l h h l h l h l h l h l h l h l h l h x llll x l l h l h h l l l l l x hh 54 3 21 0 lsb msb 54 3 21 0 lsb msb 6 7 54 3 21 0 lsb msb 6 7 x : don't care w
msm6222b-01 ? semiconductor 22/45 fedl6222b-01-01 cursor/blink control circuit this is a circuit that generates the lcd cursor and blink. this circuit is under the control of the cpu program. the display of the cursor and blink on the lcd is made at a position corresponding to the dd ram address that is set in the adc. the figure below shows an example of the cursor/blink position when the value of adc is set to "07" (hex.). (note) the cursor and blink are displayed even when the cg ram address is set in the adc. for this reason, it is necessary to inhibit the cursor and blink display while the cg ram address is set in the adc. lcd display circuit (com 1 to com 16 , seg 1 to seg 40 , l, cp, do, and df) as the msm6222b-01 provides the com signal outputs (16 outputs) and the seg signal outputs (40 outputs), it can display 8 characters (1-line display) or 16 characters (2-line display) as a unit. seg 1 to seg 40 are used to display 8-digit display on the lcd. to expand the display, an msm5259 is used. the msm5259, 40-dot segment driver, is used for expansion of the seg signal output. interface with the msm5259 is made through data output pin (do), clock output pin (cp), latch output pin (l), and display frequency pin (df). the character pattern data is serially transferred to msm5259 through do and cp. when the data of 72 characters 360-bit (= 5- bit/ch. x 72 ch. = 1-line display) or 32 characters 160-bit (5-bit/ch. x 32 ch. = 2-line display) is output, the latch pulse is also output through pin l. by this latch pulse, the data transferred serially to msm5259 is latched to be used as display data. the display frequency signal (df) required when lcd is displayed is also output from df pin synchronously with this latch pulse. l db 6 l l l adc h h h db 0 00 first digit 01 2 02 3 05 4 04 5 in 1-line display mode 05 6 06 7 07 8 7 0 08 9 4e 79 4f 80 cursor and blink position 00 first digit 01 2 02 3 03 4 04 5 first line 05 6 06 7 07 8 08 9 26 39 27 40 40 41 42 43 44 second line 45 46 47 48 66 67 cursor and blink position in 2-line display mode
msm6222b-01 ? semiconductor 23/45 fedl6222b-01-01 built-in reset circuit the msm6222b-01 is automatically initialized when the power is turned on. during initialization, the busy flag (bf) holds "h" and does not accept instructions (other than the busy flag read). the busy flag holds "h" for 15 ms after v dd reaches 4.5v or more. during initialization, the msm6222b-01 executes the follwing instructions: ? display clear ? data length of interface with cpu: 8 bits (8b/4b = "h") ? lcd: 1-line display (n = "l") ? character font: 5 x 7 dots (f = "l") ? adc: increment (i/d = "h") ? no display shift (sh = "l") ? display: off (di = "l") ? cursor: off (c = "l") ? no blink (b = "l") it is required to satisfy the following power supply conditions. fig. 1. power on/off waveform 4.5v 0.2v t on 0.2v t off 1ms t off 0.1ms t on 100ms v dd 0.2v
msm6222b-01 ? semiconductor 24/45 fedl6222b-01-01 data bus connected with cpu the data bus connected with cpu is available either once for 8 bits or twice for 4 bits. this allows the msm6222b-01 to be interfaced with either an 8-bit or 4-bit cpu. (1) when the interface data length is 8 bits data buses db 0 to db 7 (8 buses) are all used and data input/output is carried out in one step. (2) when the interface data length is 4 bits the 8-bit data input/output is carried out in two steps by using only high-order 4 bits of data buses db 4 to db 7 (4 buses) the first time data input/output is made for 4-high order bits (db 4 to db 7 when the interfaces data length is 8 bits) and the second time data input/output is made for low- order 4 bits (db 0 to db 3 when the interface data length is 8 bits). even when the data input/output can be completely made through high-order 4 bits, be sure to make another input/output of low-order 4 bits. (example: busy flag read). since the data input/output is carried out in two steps but as one execution, no normal data transfer is executed from the next input/output if accessed only once.
msm6222b-01 ? semiconductor 25/45 fedl6222b-01-01 fig. 2 8-bit data transfer rs r/w e db 7 db 1 db 2 db 3 db 4 db 5 db 6 db 0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 ir0 busy no busy adc1 adc2 adc3 adc4 adc5 adc6 adc0 dr1 dr2 dr3 dr4 dr5 dr6 dr7 dr0 instruction register(ir) write busy flag(bf)and address counter(adc)read data register (dr)write busy (internal operation)
msm6222b-01 ? semiconductor 26/45 fedl6222b-01-01 db 4 db 5 e r/w rs db 6 db 7 ir5 ir6 ir7 ir4 ir1 ir2 ir3 ir0 busy no busy adc6 adc5 adc4 adc3 adc0 adc2 adc1 dr5 dr6 dr7 dr4 dr1 dr2 dr3 dr0 fig. 3 4-bit data transfer instruction register (ir)write busy flag(bf)and address counter(adc)read data register (dr)write busy(internal operation)
msm6222b-01 ? semiconductor 27/45 fedl6222b-01-01 l r/w instruction code l rs l db 7 l db 6 l db 5 l db 4 l db 3 l db 2 l db 1 h db 0 instruction code the instruction code is defined as the signal through which the msm6222b-01 is accessed by the cpu. the msm6222b-01 begins operation upon receipt of the instruction code input. as the internal processing operation of msm6222b-01 starts in a timing that does not affect the lcd display, the busy status continues for longer than the cpu cycle time. under the busy status (when the busy flag is set to "h"), the msm6222b-01 does not execute any instructions other than the busy flag read. therefore, the cpu has to verify that the busy flag is set to "l" prior to the input of the instruction code. (1) display clear: when this instruction is executed, the lcd display is cleared. i/d in the entry mode setting is set to "h" (increment). sh does not change. when the cursor and blink are in display, the blinking position moves to the left end of the lcd (the left end of the first line in the 2-line display mode). (note) all dd ram data goes to "20" (hex.), while the address counter (adc) goes to "00" (hex.). the execution time is 1.64 ms (max.), when the osc oscillation frequency is 250 khz. (2) cursor home when this instruction is executed, the blinking position moves to the left end of the lcd (to the left end of the first line in the 2-line display mode) as the cursor and blink are being displayed. when the display is in shift, the display returns to its original position before shifting. (note) the address counter (adc) goes to "00" (hex.). the execution time is 1.64 ms (max.), when the osc oscillation frequency is 250 khz. l r/w instruction code l rs l db 7 l db 6 l db 5 l db 4 l db 3 l db 2 h db 1 x db 0 x : don't care
msm6222b-01 ? semiconductor 28/45 fedl6222b-01-01 l r/w instruction code l rs l db 7 l db 6 l db 5 l db 4 l db 3 h db 2 i/d db 1 sh db 0 (3) movement mode setting 1 when the i/d is set, the 8-bit character code is written or read to and from the dd ram, the cursor and blink shift to the right by 1 character position (i/d = "h"; increment) or to the left by 1 character position (i/d = "l"; decrement). the address counter is incremented (i/d = "h") or decremented (i/d = "l") by 1 at this time. even after the character pattern code is written or read to and from the cg ram, the address counter (adc) is incremented (i/d = "h") or decremented (i/d = "l") by 1. 2 when sh = "h" is set, the character code is written to the dd ram. then the cursor and blink stop and the entire display shifts to the left (i/d = "h") or to the right (i/ d = "l") by 1 character position. when the character is read from the dd ram during sh = "h", or when the character pattern data is written or read to or from the cg ram during sh = "h", the entire display does not shift, but normal write/read is performed (the entire display does not shift, but the cursor and blink shift to the right (i/d = "h") or to the left (i/d = "l") by 1 character position. when sh = "l" is set, the display does not shift, but normal write/read is performed. the execution time when the osc oscillation frequency is 250 khz is 40 m s. (4) display mode setting l r/w instruction code l rs l db 7 l db 6 l db 5 l db 4 h db 3 di db 2 c db 1 b db 0 1 the di bit controls whether the character pattern is displayed or not displayed. when di is "h", this bit makes the lcd display the character pattern. when di is "l", the lcd character pattern is not displayed. the cursor and blink are also cancelled at this time. (note) unlike the display clear, the character code is not rewritten at all. 2 the cursor is not displayed when c = "l" and is displayed when di = "h" and c = "h". 3 the blink is cancelled when b = "l" and is executed when di = "h" and b = "h". in the blink mode, all dots (including the cursor), displaying character pattern, and cursor are displayed alternately at 409.6 ms (in 5 x 7 dots character font) or 563.2 ms (in 5 x 10 dots character font) when the osc oscillation frequency is 250 khz. the execution time when the osc oscillation frequency is 250 khz is 40 m s.
msm6222b-01 ? semiconductor 29/45 fedl6222b-01-01 number of display lines duty ratio n l character font number of biases number of commom signals 1 - line 5 x 7 dots 1/8 8 4 l 1 - line 5 x 10 dots 1/11 11 4 h 2 - line 5 x 7 dots 1/16 16 5 h 2 - line 1/16 16 5 5 x 7 dots f l h l h (5) cursor and display shift when d/c = "l" and r/l = "l", the cursor and blink positions are shifted to the left by 1 character position (adc is decremented by 1). when d/c = l and r/l = "h", the cursor and blink positions are shifted to the right by 1 character position (adc is incremented by 1). when d/c = "h" and r/l = "l", the entire display is shifted to the left by 1 character position. the cursor and blink positions are also shifted with the display (adc remains unchanged). when d/c = "h" and r/l = "h", the entire display is shifted to the right by 1 character position. the cursor and blink positions are also shifted with the display (adc remains unchanged). in the 2-line display mode, the cursor and blink positions are shifted from the first to the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.) in the first line. no such shifting is made in other cases. when shifting the entire display, the display pattern, cursor, and blink positions are in no case shifted between lines (from the first to the second line or vice versa). the execution time, when the osc oscillation frequency is 250 khz, is 40 m s. (6) initial setting 1 when 8b/4b = "h", the data input/output to and from the cpu is carried out simultaneously by means of 8 bits db 7 to db 0 . when 8b/4b = "l", the data input/output to and from the cpu is carried out in two steps through 4 bits of db 7 to db 4 . 2 the 2-line display mode of the lcd is selected when n = "h", while the 1-line display mode is selected when n = "l". 3 the 5 x 7 dots character font is selected when f = "l", while the 5 x 10 dots character font is selected when f = "h" and n = "l". this initial setting has to be accessed prior to other instructions except for the busy flag read after the power is supplied to the msm6222b-01. l r/w instruction code l rs l db 7 l db 6 l db 5 h db 4 d/c db 3 r/l db 2 x db 1 x db 0 x : don't care l r/w instruction code l rs l db 7 l db 6 h db 5 8b/4b db 4 n db 3 f db 2 x db 1 x db 0 x : don't care
msm6222b-01 ? semiconductor 30/45 fedl6222b-01-01 generate biases externally and input them to the msm6222b-01 (v dd , v 1 , v 2 , v 3 , v 4 , and v 5 ). when the number of biases is 4, input the same potential to v 2 and v 3 . the execution time, when the osc oscillation frequency is 250 khz, is 40 m s. (7) cg ram address setting l r/w instruction code l rs l db 7 h db 6 c 5 db 5 c 4 db 4 c 3 db 3 c 2 db 2 c 1 db 1 c 0 db 0 l r/w instruction code h rs e 7 db 7 e 6 db 6 e 5 db 5 e 4 db 4 e 3 db 3 e 2 db 2 e 1 db 1 e 0 db 0 l r/w instruction code l rs h db 7 d 6 db 6 d 5 db 5 d 4 db 4 d 3 db 3 d 2 db 2 d 1 db 1 d 0 db 0 when cg ram addresses, bits c 5 to c 0 (binary), are set, the cg ram is specified, until the dd ram address is set. write/read of the character pattern to and from the cpu begins with addresses, bits c 5 to c 0 , starting from cg ram selection. the execution time, when the osc oscillation frequency is 250 khz, is 40 m s. (8) dd ram address setting when the dd ram addresses d 6 to d 0 (binary) are selected, the dd ram is specified until the dd ram address is set. write/read of the character code to and from the cpu begins with addresses d 6 to d 0 starting from dd ram selection. in the 1-line display mode (n = h), however, d 6 to d 0 (binary) must be set to one of the values among "00" to "4f" (hex.). likewise, in the 2-line mode, d 6 to d 0 (binary) must be set to one of the values among "00" to "27" (hex.) or "40" to "67" (hex.). when any value other than the above is input, it is impossible to make a normal write/ read of character codes to and from the dd ram. the execution time, when the osc oscillation frequency is 250 khz, is 40 m s. (9) dd ram and cg ram data write when e 7 to e 0 (binary) codes are written to the dd ram or cg ram, the cursor and display move as described in "(5) cursor and display shift". the execution time, when the osc oscillation frequency is 250 khz, is 40 m s.
msm6222b-01 ? semiconductor 31/45 fedl6222b-01-01 h r/w instruction code l rs bf db 7 o 6 db 6 o 5 db 5 o 4 db 4 o 3 db 3 o 2 db 2 o 1 db 1 o 0 db 0 h r/w instruction code h rs p 7 db 7 p 6 db 6 p 5 db 5 p 4 db 4 p 3 db 3 p 2 db 2 p 1 db 1 p 0 db 0 (10) busy flag and address counter read (execution time is 1 m s.) the busy flag (bf) is output by this instruction to indicate whether the msm6222b-01 is engaged in internal operations (bf = "h") or not (bf = "l"). when bf = "h", no new instruction is accepted. it is therefore necessary to verify bf = "l" before inputting a new instruction. when bf = "l", a correct address counter value is output. the address counter value must match the dd ram address or cg ram address. the decision of whether it is a dd ram address or cg ram address is made by the address previously set. since the address counter value when bf = "h" is sometimes incremented or decremented by 1 during internal operations, it is not always a correct value. (11) dd ram and cg ram data read character codes (bits p 7 to p 0 ) are read from the dd ram, while character patterns (p 7 to p 0 ) from the cg ram. selection of dd ram or cg ram is decided by the address previously set. after reading those data, the address counter (adc) is incremented or decremented by 1 as set by the shift mode mentioned in item "(3) shift mode set". the execution time, when the osc oscillation frequency is 250 khz, is 40 m s. (note) conditions for the reading of correct data: 1 when the dd ram address set or cg ram address set is input before inputting this instruction. 2 when the cursor/display shift is input before inputting this instruction in case the character code is read. 3 data after the second reading from ram when read more than 2 times. correct data is not output in any other case.
msm6222b-01 ? semiconductor 32/45 fedl6222b-01-01 interface with lcd and msm5259 display examples when setting the 5 x 7 dots character font 1-line mode, 5 x 10 dots character font 1-line mode, and 5 x 7 dots character font 2-line mode through instructions are shown in figures 4, 5, and 6, respectively. when the 5 x 7 dots character font is set in the 1-line display mode, the com signals com 9 to com 16 are output for extinguishing. likewise, when the 5 x 10 dots character font (1-line is set), the com signals com 12 to com 16 are output for display-off. the display example shows a combination of 16 characters (32 characters for the 2-line display mode) and the lcd. when the number of msm5259s are increased according to the increase in the number of characters, it is possible to display a maximum of 80 characters. besides, it is necessary to generate bias voltage required for lcd operation by splitting resistors outside the ic to input it to msm6222b-01 and msm5259. examples of these bias voltages are shown in figures 7, 8, 9, and 10. basically, this can be done by dividing the voltage by the resistors as shown in figures 7 and 8. if the value of resistor r is made larger to reduce system power consumption, the lcd operating margin decreases and the lcd driving waveform is distorted. to prevent this, a by-pass capacitor is serially connected to the resistor to lower voltage division impedance caused by the splitting of resistors as shown in figures 9 and 10. as the values of r, vr, and c vary according to the lcd size used and v lcd (lcd drive voltage), these values have to be determined through actual experimentation in combination with the lcd. (example set values: r = 3.3 to 10k w , v r = 10 to 30k w , and c = 0.0022 m f to 0.047 m f) figure 17 shows an application circuit for the msm6222b-01 and msm5259 including a bias circuit. the bias voltage has to maintain the following potential relation: v dd > v 1 > v 2 3 v 3 > v 4 > v 5 figure 4 ? in the case of 1-line 16 characters display (5 x 7 dots/font) com 1 seg 1 seg 40 o 1 o 40 msm6222b-01 do cp df l di 1 cp msm5259 df load do 20 di 21 lcd com 8
msm6222b-01 ? semiconductor 33/45 fedl6222b-01-01 ? in the case of 16-character (1 line) display (5 x 10 dots/font) figure 5 ? in the case of 16-character (2 lines) display (5 x 7 dots/font) figure 6 com 1 com 15 seg 1 seg 40 o 1 o 40 msm6222b-01 do cp df l di 1 cp msm5259 df load do 20 di 21 com 8 com 7 com 16 com 9 lcd com 1 com 11 seg 1 seg 40 o 1 o 40 msm6222b-01 do cp df l di 1 cp msm5259 df load do 20 di 21 lcd
msm6222b-01 ? semiconductor 34/45 fedl6222b-01-01 ? bias voltage circuit (1-line display mode) ? bias voltage circuit (2-line display mode) (v lcd : lcd driving voltage) ? bias voltage circuit (1-line display mode) ? bias voltage circuit (2-line display mode) v lcd r r r r vr v dd v 1 v 2 v 3 v 4 v 5 msm6222b-01 v lcd r r r r vr v dd v 1 v 2 v 3 v 4 v 5 msm6222b-01 v lcd r r r r v dd v 1 v 2 v 3 v 4 v 5 vr c c c c c msm6222b-01 v lcd r r r r vr v dd v 1 v 2 v 3 v 4 v 5 rc c c c c msm6222b-01 c figure 7 figure 8 figure 9 figure 10
msm6222b-01 ? semiconductor 35/45 fedl6222b-01-01 ? application circuit figure 11 +5v r c r c r c r c r c vr c 0v do cp seg 1 - 40 com 1 - 16 l df v 1 v 2 v 3 v dd gnd v 4 v 5 msm6222b-01 o 1 - o 40 msm5259 o 1 - o 40 msm5259 o 1 - o 40 msm5259 di 1 cp load do 40 do 20 di 21 df v dd v ss v 2 v 3 v ee lcd di 1 cp load do 40 do 20 di 21 df v dd v ss v 2 v 3 v ee di 1 cp load do 40 do 20 di 21 df v dd v ss v 2 v 3 v ee
msm6222b-01 ? semiconductor 36/45 fedl6222b-01-01 lcd drive waveforms figures 12, 13 and 14 show the lcd driving waveforms consisting of com signal, seg signal, df signal and l (latch pulse waveform) signal, in the duty of 1/8, 1/11 and 1/16 respectively. the relation between duty and frame frequency is described in the table below. (note) the osc oscillation frequency is assumed to be 250 khz. duty 1/8 78.1 hz frame frequency 1/11 56.8 hz 1/16 78.1 hz
msm6222b-01 ? semiconductor 37/45 fedl6222b-01-01 figure 12. lcd driving waveform at 1/8 duty 81234567812 com 1 com 2 com 8 com 9 com 16 df l seg (output example) 1 frame v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd display-on waveform display-off waveform
msm6222b-01 ? semiconductor 38/45 fedl6222b-01-01 figure 13. lcd driving waveform at 1/11 duty com 1 com 2 com 16 df l com 11 com 12 11123456789101112 seg (output example) v 2 ,v 3 v 1 v 4 v 5 v v v v dd 1 frame v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd v 2 ,v 3 v 1 v 4 v 5 v v v v dd display-on waveform display-off waveform
msm6222b-01 ? semiconductor 39/45 fedl6222b-01-01 figure 14. lcd driving waveform at 1/16 duty 1612 345 6 7891011 com 1 com 2 com 16 df l 13 14 15 16 1 2 12 seg (output example) v 2 v 1 v 3 v 4 v v v dd v 5 1 frame v 2 v 1 v 3 v 4 v v v dd v 5 v 2 v 1 v 3 v 4 v v v dd v 5 v 2 v 1 v 3 v 4 v v v dd v 5 display-off waveform display-on waveform
msm6222b-01 ? semiconductor 40/45 fedl6222b-01-01 l r/w l rs l db 7 l db 6 h db 5 h db 4 x db 3 x db 2 x db 1 x db 0 x : don't care initial setting of instruction (1) when data input/output to and from the cpu is carried out by 8 bits (db 0 to db 7 ): q turn on the power. w wait for 15 ms or more after v dd has reached 4.5v or more. e set 8b/4b at "h" by initial setting of instruction. r wait for 4.1 ms or more. t set 8b/4b at "h" by initial setting of instruction. y wait for 100 m s or more. u set 8b/4b at "h" by initial setting of instruction. i check the busy flag as no busy. o set 8b/4b at "h". set lcd line number (n) and character font (f). (after this, do not change the lcd line number and character font.) !0 check no busy. !1 clear the display by setting the display mode. !2 check no busy. !3 clear the display. !4 check no busy. !5 set the shift mode. !6 check no busy. !7 initial setting completed. example of instruction code for steps e , t , and u .
msm6222b-01 ? semiconductor 41/45 fedl6222b-01-01 (2) when data input/output to and from the cpu is carried out by 4 bits (db 4 to db 7 ): q turn on the power. w wait for 15 ms or more after v dd has reached 4.5v or more. e set 8b/4b at "h" by initial setting of instruction. r wait for 4.1 ms or more. t set 8b/4b at "h" by initial setting of instruction. y wait for 100 m s or more. u set 8b/4b at "h" by initial setting of instruction. i check the busy flag as no busy. o set 8b/4b at "l". set lcd line number (n) and character font (f). !0 wait for 100 m s or more. !1 set 8b/4b at "l". set lcd line number (n) and character font (f). !2 check no busy. !3 clear the display by setting the display mode. !4 check no busy. !5 clear the display. !6 check no busy. !7 set the shift mode. !8 check no busy. !9 initialization completed. example of instruction code for steps e , t , and u . example of instruction code for step i . example of instruction code for step o . execute two-step accesses in 4 bits from step !1 to step !8 . l r/w l rs l db 7 l db 6 h db 5 h db 4 l r/w l rs l db 7 l db 6 h db 5 l db 4 h r/w l rs bf db 7 o 6 db 6 o 5 db 5 o 4 db 4
msm6222b-01 ? semiconductor 42/45 fedl6222b-01-01 differences between hd44780 and msm6222b-xx hd44780 msm6222b - 01 item lcd driving voltage (v lcd ) the increment and decrement of the address counter in writing/ reading the data to/from the cgram/ddram. 1/4 bias 1/5 bias 3.0 to 11.0 (v) 4.6 to 11.0 (v) 3.0 to 8.0 (v) 3.0 to 8.0 (v) bus interface speed with cpu 1 mhz (1000 ns) 1.5 mhz (667 ns) since signal rise/fall time is quite fast, the electromagnetic induction between lines of the pcb and the cable assignment should be noted. the address counter is incremented or decremented 6 m sec (when ? osc = 250 khz) after the busy condition is released. (period of busy condition is 40 m s) so, the data cannot be written into/ read out from the ram for 6 m sec after the busy condition was over. the address counter is incremented or decremented during the busy condition. so, data can be written into/read out from the ram immediately after the busy condition was over. the repeated input frequency (oscillation frequency=250khz) of display clear instruction 610 hz or less (1.64 ms or more) 78 hz or less in 5 7 dots (12.8 ms or more), 56hz or less in 5 10 dots (17.9 ms or more)
msm6222b-01 ? semiconductor 43/45 fedl6222b-01-01 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-l package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. spherical surface
msm6222b-01 ? semiconductor 44/45 fedl6222b-01-01 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bl package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. spherical surface
msm6222b-01 ? semiconductor 45/45 fedl6222b-01-01 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2001 oki electric industry co., ltd. printed in japan

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